Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-04-18

1998-10-27

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, G11C 1406

Patent

active

058286195

ABSTRACT:
In a DRAM, an external cycle count circuit detects an operation cycle of a signal RAS which is externally inputted, and a signal expressing the result is outputted to a CBR signal generating circuit and a self refresh signal generating circuit. In response to outputs from the respective signal generating circuits, an internal RAS signal generating circuit outputs a refresh instruction signal INRAS for CBR refresh and self refresh. For self refresh, as the operation cycle of the signal RAS immediately before self refresh begins, a refresh cycle is set longer. For CBR refresh, when the operation cycle of the signal RAS is long, a CBR refresh instruction signal is generated in accordance with only a part of an operation of the signal RAS. By reducing the frequency of refresh, consumption power is reduced. By means of control which considers a parameter which influences an internal temperature of a semiconductor memory device such as a DRAM, consumption power is reduced and an operation speed is improved.

REFERENCES:
patent: 5321662 (1994-06-01), Ogawa
patent: 5495452 (1996-02-01), Cha
patent: 5515331 (1996-05-01), Kim
IBM Technical Disclosure Bulletin, vol. 33, No. 2, Jul. 1990, pp. 68-72,, "Intelligent DRAM Refresh Controller".

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