Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1986-07-22

1988-09-06

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Semiconductive

365189, G11C 1134

Patent

active

047697873

ABSTRACT:
Using a comparatively low supply voltage of, e.g., +5V and a minus gate voltage, the voltage difference between the gate of an MNOS transistor and a P-type well region in which a MNOS transistor is formed is relatively changed to execute the writing and erasing of the MNOS transistor. Thus, the potential of an N-type semiconductor substrate can be fixed to a comparatively low potential, e.g., about +5V, so that a P-channel MOSFET formed on the semiconductor substrate operates with an ordinary signal level. Consequently, an EEPROM having peripheral circuits constructed of CMOS circuits can be provided. Accordingly, reduction in the power consumption of the EEPROM can be attained.

REFERENCES:
patent: 4480321 (1984-10-01), Aoyama
patent: 4630086 (1986-12-01), Sato et al.
K. Uchiumi, "16K Bit EEPROM Having the Character of Access Time 350 ns and Power Dissipation 300 mW" Nikkei Electronics, Jul. 6, 1981, pp. 193-206.

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