Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1989-03-27

1991-01-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 3652257, G11C 700, G11C 2900

Patent

active

049875604

ABSTRACT:
A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line in response to an output from the NAND gate, a fuse element connected between the output terminal of the NAND gate and the input terminal of the inverter, and a MOS transistor connected between the input terminal of the inverter and a power supply voltage.

REFERENCES:
patent: 4587638 (1986-05-01), Isobe et al.
patent: 4829481 (1989-05-01), Johnson et al.
Sakurai et al., "A Low Power 46 ns 256 kbit CMOS Static RAM with Dynamic Double Word Line," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 578-585, Oct. 1984.

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