Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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G11C 700

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active

045717060

ABSTRACT:
A semiconductor memory device is disclosed in which, when a main memory contains an error bit cell, the main memory is switched to an auxiliary memory by cutting off an interconnection wire between a decoder and the main memory, and subjecting a high resistance polysilicon connected between the decoder and the auxiliary memory to laser annealing to reduce the resistance of the high resistance polysilicon and to connect the decoder and the auxiliary memory.

REFERENCES:
patent: 3940740 (1976-02-01), Coontz
patent: 4399372 (1983-08-01), Tanimoto et al.
Kokkonen et al., "Redundancy Techniques for Fast Static RAMs", ISSCC Digest of Technical Papers, pp. 80-81, Feb. 18, 1981.

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