Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1985-08-05

1987-07-14

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365149, G11C 700

Patent

active

046807349

ABSTRACT:
A semiconductor memory device having a data inverting circuit for selectively inverting an input/outpt data of a sense amplifier in such a way that the charging states of respective memory cells connected to two bit lines in each bit line pair become equal for the same input/output data. A clamp circuit draws the potentials of all of the bit lines to a predetermined potential in response to a clear control signal, whereby the contents of all of the memory cells are cleared at the same time.

REFERENCES:
patent: 4386419 (1983-05-01), Yamamoto
patent: 4479202 (1984-10-01), Uchida
K. S. Gray et al., "Block Erase for One-Device Cell Memory Arrays", IBM Technical Disclosure Bulletin, vol. 20, No. 5, Oct. 1977, pp. 1716-1717.

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