Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

36518905, 365226, 365 51, 365 63, G11C 800, G11C 700, G11C 502, G11C 506

Patent

active

057712000

ABSTRACT:
A semiconductor memory device reduces the distance occupied between a data path circuit and pads, and minimizes the length of data lines and main input/output lines, thereby improving an operating speed thereof. The semiconductor memory device includes a memory array divided into four array blocks which are independently arranged; a plurality of pads disposed in an area between the upper array blocks and the respective lower array blocks; a data path control circuit disposed in an area between the left array blocks and the respective right array blocks; a data path circuit disposed in a middle center area among the four array blocks; a plurality of data lines connecting the pads to the data path circuit; and a plurality of main input/output lines connecting the memory array to the data path circuit. In this configuration, a distance between the data lines and the main input/output lines and the data path circuit can be minimized.

REFERENCES:
patent: 4731761 (1988-03-01), Kobayashi
patent: 5109265 (1992-04-01), Utesch et al.
patent: 5150330 (1992-09-01), Hag
patent: 5378925 (1995-01-01), Sasaki
patent: 5416347 (1995-05-01), Katto et al.

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