Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1998-04-30
1999-06-29
Mai, Son
Static information storage and retrieval
Read/write circuit
Bad bit
36518907, G11C 700
Patent
active
059177640
ABSTRACT:
A semiconductor memory device comprises a memory cell array, a redundancy memory cell array provided as a reserve for the memory cell array, a redundancy calculation and allocation circuit, whenever a test circuit for successively testing a plurality of memory cells forming the memory cell array has found a failure memory cell, for generating at least one repair solution for repairing the failure memory cell in parallel to the test of the plurality of memory cells carried out by the test circuit, and a redundancy circuit for substituting a row or a column of the memory cell array by a row or a column of the redundancy memory cell array on the basis of the at least one repair solution.
REFERENCES:
patent: 5748543 (1998-05-01), Lee et al.
Maejima Hiroshi
Ohsawa Takashi
Kabushiki Kaisha Toshiba
Mai Son
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