Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-12-21
1995-12-26
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 327526, G11C 700
Patent
active
054793718
ABSTRACT:
There is disclosed a semiconductor memory device comprising a plurality of blocks in which memory cells are respectively arranged on a plurality of normal rows and one spare row. Each block includes a plurality of normal row selection lines for selecting any one of the normal rows, and one spare row selection line for instead selecting the spare row in the case where any one of the normal rows is defective. The device further comprises non-selection circuit elements provided for every normal row selection line, and being such that when a corresponding normal row is defective, the non-selection circuit element allows that defective normal row selection line to be brought into non-selective state; and a selector adapted so that when the normal rows in a corresponding block are all in non-selective state, the selector allows the spare row selection line to be brought into selective state. Also, with respect to a column direction, a circuit configuration similar to the above may be provided.
REFERENCES:
patent: 4571706 (1986-02-01), Iwahashi et al.
patent: 4587638 (1986-05-01), Isobe et al.
patent: 4604730 (1986-08-01), Yoshida et al.
patent: 4791319 (1988-12-01), Tagami et al.
patent: 5134585 (1992-07-01), Murakami et al.
patent: 5282165 (1994-01-01), Miyake et al.
Dinh Son
Kabushiki Kaisha Toshiba
Nelms David C.
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