Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1993-08-24

1994-06-14

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

365210, 365233, G11C 700

Patent

active

053216555

ABSTRACT:
There is disclosed a semiconductor memory device comprising memory cells (M11 to Mnn) for storing binary data, and first reference cells (DM11 to Dm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.

REFERENCES:
patent: 4301518 (1981-11-01), Klaas
patent: 5148063 (1992-09-01), Hotta
patent: 5197030 (1993-03-01), Akaogi et al.
patent: 5218572 (1993-06-01), Lee et al.
Richard Zeman et al., "A 55ns CMOS EEPROM", IEEE ISSCC Digest of Technical Papers, pp. 144-145, 1984.

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