Semiconductor memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Patent

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Details

36518902, 365201, G11C 800

Patent

active

059635002

ABSTRACT:
A decoder circuit selectively controls the transfer gate group. The transfer gate group is stacked so as to form a tree structure having multiple stages of transfer gates and enable a monitoring bus line to be connected to any column in a memory cell array. This configuration enables the current in each memory cell to be monitored at an external pad via a single bus line, which reduces the area occupied by the bus lines, suppressing an increase in the chip size.

REFERENCES:
patent: 5124949 (1992-06-01), Morigami

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