Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Testing

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Details

36518707, 365200, 36520306, G11C 700, G11C 2900

Patent

active

053595610

ABSTRACT:
A semiconductor memory device is provided which includes a plurality of data lines, at least one redundant data line, one common data line, a plurality of column switches installed between the plurality of data lines and the redundant data line and one common data line, and a column decoder for controlling the plurality of column switches. The column decoder operates to turn the column switch on. The column switch is connected to a plurality of data lines, excluding any defective data and redundant data lines during the test mode state.

REFERENCES:
patent: 4811299 (1989-03-01), Miyazawa et al.
patent: 4860260 (1989-08-01), Saito et al.
patent: 4916700 (1990-04-01), Ito et al.
patent: 4918662 (1990-04-01), Kondo
patent: 4991139 (1991-02-01), Takahashi et al.

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