Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1992-09-10

1994-04-19

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

G11C 1140

Patent

active

053052730

ABSTRACT:
A semiconductor memory device has a matrix of memory cells interconnected by a plurality of column and row lines to form a channel between one of the column lines and a voltage source corresponding to a specified status. A sensing circuit connects or disconnects an output node where the current is supplied from the voltage source with the input node which indicates the status of the specified memory cell. A reference voltage generation circuit generates the reference voltage. A comparison circuit generates a signal to indicate the specified status of the selected memory cell. Between the output and input nodes of the sensing circuit, a first transistor under gate control by a reverse voltage of the input node voltage is connected and between the input node of the sensing circuit and the input node of the reference voltage generation circuit, a second transistor under gate control by the reverse voltage is also provided. The column line of the selected memory cell is charged by the voltage source of the sensing circuit via the first transistor and also by the voltage source of the reference voltage generation circuit via the second transistor.

REFERENCES:
patent: 4802138 (1989-01-01), Shimamune
patent: 4974207 (1990-11-01), Hashimoto
patent: 5040148 (1991-08-01), Nakai

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