Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1994-05-25

1995-05-02

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Differential sensing

365205, 327 51, G11C 1140

Patent

active

054126070

ABSTRACT:
A semiconductor memory device according to the present invention includes a first and second bit lines; a word line; a memory cell electrically connected to the first and second bit lines and the word line; a first current sense amplifier for reducing a potential level of a current flowing in the first and second bit lines and including diode-connected first and second P-type transistors, third and fourth N-type transistors series-connected to the first and second P-type transistors respectively and a fifth N-type transistor connected to the third and fourth N-type transistors, the first P-type transistor having a control electrode electrically connected to a control electrode of the fourth N-type transistor and the second P-type transistor having a control electrode electrically connected to a control electrode of the third N-type transistor; and a second sense amplifier electrically connected to an output of the first current sense amplifier, for amplifying the amplitude of a potential applied between the first and second bit lines.

REFERENCES:
patent: 5111429 (1992-05-01), Whitaker
patent: 5325335 (1994-06-01), Ang et al.
patent: 5353249 (1994-10-01), Itano
patent: 5353255 (1994-10-01), Komuro
Katsuro Sasaki et al., "A 7-ns 140-mW CMOS SRAM with Current Sense Amplifier", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1511-1517.

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