Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1997-06-16

1998-08-18

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518901, 36523006, 36518903, G11C 1100

Patent

active

057966591

ABSTRACT:
A SRAM 100, 200 has dedicates address decoders 1 and 2 to select a memory cell 5 in write-in operation, and dedicates address decoders 3 and 4 to select a memory cell 5 during readout operation, and memory cells 5. Only one memory cell 5 is connected to the write-in data line 14 in the write-in operation and to the readout data line 11 in the readout operation, respectively, under the control of the dedicated address decoders.

REFERENCES:
patent: 5365482 (1994-11-01), Nakayama
patent: 5406526 (1995-04-01), Sugibayashi et al.
patent: 5465234 (1995-11-01), Hannai
patent: 5691950 (1997-11-01), McClure
patent: 5706244 (1998-01-01), Shimizu

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1121491