Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Semiconductive

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36518909, 36518911, 365218, G11C 1134

Patent

active

050220004

ABSTRACT:
A writing high voltage of one polarity or an erasing high voltage of another polarity is selectively fed, in accordance with a writing or erasing operation mode, via a switch MOSFET to the word line of a non-volatile memory element designated by an address signal. The potential of a well region, where the switch MOSFET is existent, is changed in conformity with the switching action of the relevant switch MOSFET so as to control the switch MOSFET. Due to this arrangement, the potential of the well region with the non-volatile memory elements existing thereon can be retained at a fixed value, so that the high voltage generator is required merely to drive the selected word line of the memory array (and not the well in which the memory elements are formed). Consequently, the requisite current supply capability of the high voltage generator can be diminished.

REFERENCES:
patent: 4769787 (1988-09-01), Furusawa et al.
Nikkei Electronics 1986 (No. 388), pp. 142-145, "64 Kbit Peripheral CMOS EEPROMs".

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