Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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365189, G11C 1140, G11C 1300

Patent

active

047291176

ABSTRACT:
A semiconductor memory device is comprised of memory cells arranged in a matrix fashion; defective row line detect circuits for producing logic "1" when a defective row line is selectd to which a detective cell is connected; defective column line detect circuits for producing a logical "1" signal when a defective column line is selected to which a defective cell is connected; an AND gate for detecting the selection of defective cell using a logic value of the output signals from defective row and column line detect circuits; and an exclusive OR gate for exclusively ORing the read out data signal and the output signal from the AND gate to correct the defective data.

REFERENCES:
patent: 4485471 (1984-11-01), Singh et al.
patent: 4592024 (1986-05-01), Sakai et al.

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