Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1984-02-08
1986-08-05
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Bad bit
G11C 700
Patent
active
046047301
ABSTRACT:
A semiconductor memory device includes a plurality of memory cell blocks corresponding to output terminals, and a redundancy memory cell block for replacing a faulty memory cell block among the memory cell blocks, the redundancy memory cell block having a first specific area for storing a first predetermined data of electronic signatures. Each of the memory cell blocks having a second specific area for storing a second predetermined data equal to a divided one of the first predetermined data in a one to one correspondence. The semiconductor memory device further includes a circuit for selectively reading, when one of the memory cell blocks is replaced by the redundancy memory cell block, a divided one of the first predetermined data corresponding to the second predetermined data stored inthe memory cell block to be replaced by the redundancy memory cell block. The second predetermined data can be correctly read out even when a faulty memory cell block is replaced with the redundancy memory cell block.
REFERENCES:
patent: 4460998 (1984-07-01), Yamada et al.
patent: 4471472 (1984-09-01), Young
IEEE International Solid-State Circuits Conference, "Redundancy Techniques for Fast Static RAMs", Kokkonen et al., ISSCC 81, 2/18/81, pp. 80-81.
IEEE International Solid-State Circuits Conference, "A 128K EPROM with Redundancy", Spaw et al., ISSCC 82, 2/11/82, pp. 112-113.
Itano Kiyoshi
Yoshida Masanobu
Fujitsu Limited
Moffitt James W.
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