Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1997-11-25

1999-07-27

Phan, Trong

Static information storage and retrieval

Read/write circuit

Bad bit

36518905, 36523003, G11C 700, G11C 1604, G11C 800

Patent

active

059301830

ABSTRACT:
According to the present invention, there is provided a semiconductor memory device comprising a memory cell array and a redundant memory cell array in which a defective cell in the memory cell array is substituted by a cell in the redundant memory cell array; further comprising: a PROM circuit in which a redundant address corresponding to the defective cell is recorded; a redundant address data holding circuit that holds the data of the redundant address recorded in the PROM circuit on initialisation; a circuit for deciding on redundancy that compares the data held by the redundant address data holding circuit with an address supplied from outside and makes a decision; and a driver circuit for the memory cell array that is actuated in accordance with the result of this decision by the circuit for deciding on redundancy and a driver circuit for the redundant memory cell array. Since a semiconductor memory device as above does not have a PROM circuit that delays the operation in the circuit for deciding on redundancy, high-speed operation of the circuit for deciding on redundancy can be achieved. As a result, overall access time can be reduced.

REFERENCES:
patent: 4748594 (1988-05-01), Iida
patent: 5097447 (1992-03-01), Ogawa et al.
patent: 5357458 (1994-10-01), Yu et al.
patent: 5359560 (1994-10-01), Suh et al.
patent: 5485424 (1996-01-01), Kawamura
patent: 5617364 (1997-04-01), Hatakeyama

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