Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

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365203, G11C 700

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active

044438680

ABSTRACT:
Disclosed is a dynamic-type semiconductor memory device including a group of sense amplifiers, a plurality of pairs of bit lines extending from the sense amplifiers, and a plurality of dynamic-type memory cells connected to each bit line. Each pair of bit lines are short circuited and then precharged to a high potential level before a read operation. According to the present invention, a control line for activating the sense amplifiers is also used as a control line for short circuiting and precharging each pair of bit lines, resulting in a high degree of integration and a high short-circuiting speed.

REFERENCES:
patent: 4028557 (1977-06-01), Wilson
patent: 4122549 (1978-04-01), Kinoshita
patent: 4158241 (1979-06-01), Takemae et al.
WO81/03572, Semiconductor Memery Precharge Circuit, Proebsting, published 12/10/81, filed 6/2/80.
Gray, "Bitline Restore Shorting Technique," IBM Tech. Disc. Bul., vol. 20, No. 5, 10/77, pp. 1714-1715.
Patents Abstracts of Japan, vol. 3, No. 30, Mar. 1979, p. 66 E 97; & JP-A-54 8430 (Nippon Denki K.K.)(22-01-1979)*Abstract*.
IEEE International Solid-State Circuits Conference, vol. 18, Feb. 13, 1975, p. 1020103, New York; Foss et al.; "Simplified Peripheral Circuits for a Marginally Testable 4K RAM", p. 102, col. 1, last paragraph, FIG. 2a.

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