Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1991-09-03

1994-05-17

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

36518904, 36523009, G11C 1300

Patent

active

053134230

ABSTRACT:
A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

REFERENCES:
patent: 3402398 (1968-09-01), Koerner et al.
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4658377 (1987-04-01), McElroy
patent: 4701887 (1987-10-01), Ogawa
patent: 4989181 (1991-01-01), Harada
patent: 5115413 (1992-05-01), Sato et al.
Nishiyama, "Redundancy Circuit for Serial Read/Write Memory" NEC Corp, Patent Abstracts of Japan Jan. 18, 1989.

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