Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1983-05-23
1987-01-27
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Bad bit
G11C 700
Patent
active
046398953
ABSTRACT:
A semiconductor memory device is comprised of: a semiconductor memory having a plurality of memory cells arrayed in a matrix, a memory area of the memory including a main memory section and an auxiliary memory section; a plurality of row lines for selecting the memory cells connected to the memory cells; a plurality of power source lines provided corresponding to the row lines; and a circuit for separating or disconnecting from a power source the power source lines connected to the memory cells in an unused memory area of the semiconductor memory.
REFERENCES:
patent: 4354217 (1982-10-01), Mahon
patent: 4392211 (1983-07-01), Nakano et al.
patent: 4473895 (1984-09-01), Tatematsu
Kokkonen et al., "Redundancy Techniques for Fast Static RAMs," ISSCC Digest of Technical Papers, pp. 80-81, Feb. 18, 1981.
Iwahashi Hiroshi
Ochii Kiyofumi
Moffitt James W.
Tokyo Shibaura Denki Kabushiki Kaisha
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