Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1993-06-21

1995-02-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 3652257, G11C 11407, G11C 2900

Patent

active

053943686

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a semiconductor memory device having a defective bit relieving circuit.
2. Background Information
A defective bit relieving circuit (redundancy circuit) replaces a defective memory cell with a spare memory cell and is very convenient for improving the production yield of a semiconductor memory.
Accordingly, the redundancy circuit is currently widely used in many semiconductor memories and is disclosed in various publications such as Japanese Patent Laid-Open Publication No. 1-229498 issued on Sep. 13, 1989 and U.S. Pat. No. 4,346,459 issued on Aug. 24, 1982.
The present invention, described below, should be understood together with the known redundancy circuits as disclosed in these publications. The object of the present invention is to provide a redundancy circuit which is more flexible than that disclosed in these publications.


SUMMARY OF THE INVENTION

To achieve the above object, the semiconductor device according to the invention employs a main select line group having first and second select lines, a redundancy select line group having third and fourth select lines, a first select line activation circuit for activating one of the select lines in the main select line group in response to first and second signals, wherein the first select line activation circuit can activate the first select line when the first control signal is at a first potential level and activate the second select line when the first control signal is at a second potential level, a second select line activation circuit for activating one of the select lines in the redundancy select line group in response to the first and second control signals, wherein the first select line activation circuit can activate the third select line when the first control signal is at the first potential level and activate the fourth select line when the first control signal is at the second potential level, a first conductive line having a first terminal which receives either the first control signal or a signal having substantially the same potential level as that of the first control signal, a first node coupled to the first terminal and a first conductive portion connecting between the first terminal and the first node, a first potential supply circuit for causing the first node to be at substantially either the same potential level as that of the first or second potential level when the first conductive portion is blown, a second conductive line having a second terminal which receives a third control signal which has a complementary relationship with the first control signal, a second node coupled to the second terminal and a second conductive portion connecting between the second terminal and the second node, a second potential supply circuit for causing the second node to be at substantially the same potential level as that of the first or second potential level when the second conductive portion is blown, and a control signal generating circuit for outputting the second control signal to the second select line activation circuit when the first node and the second node have a predetermined relation to each other, and outputting the second control signal to the first select line activation circuit otherwise.
The present application discloses other various aspects of the inventions for achieving the object set forth above which will be understood from claims and various embodiments, described hereinafter and in the drawings.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a first embodiment of the present invention;
FIG. 2 is a circuit diagram of a row driver RDr in FIG. 1;
FIG. 3 is a circuit diagram of a circuit for generating row line drive signals in FIG. 1;
FIG. 4 is a timing chart of each signal in FIG. 1;
FIG. 5 is a circuit diagram of a row decoder in FIG. 1;
FIG. 6 is a circuit diagram of a second embodiment of the present invention;
FIGS. 7 and 8 are views of first and second modific

REFERENCES:
patent: 4346459 (1982-08-01), Sud et al.
patent: 4672581 (1987-06-01), Waiker

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