Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-02-03

1999-12-07

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

257347, 257369, H01L 2711

Patent

active

059988797

ABSTRACT:
In a CMOS SRAM cell formed on an SOI substrate and including a flip-flop having first and second NMOS and PMOS transistors, transfer gates having first and seconf MOS transistors, and a word line section, characterized in that:the word line section extends along a predetermined direction; that source and drain diffusion layer regions of the first and second NMOS and PMOS transistors are arranged along the predetermined direction, and gates of these NMOS and PMOS transistors are arranged on channel regions thereof in a direction perpendicular to the predetermined direction; that the gates of the first and second NMOS transistors are electrically connected to the gates of the first and second PMOS transistors, respectively; and that in regions between the gates of the first and second NMOS transistors on the channel regions and the gates of the first and second PMOS transistors on the channel regions, each of the drain diffusion layer regions of the fisrt and second NMOS and PMOS transistors, and each one of the drain and source diffusion layer regions of the first and second MOS transistors are respectively arranged to be adgacent to each other and are electrically connected to each other, respectively, through a diffusion layer interconnection.

REFERENCES:
patent: 5526303 (1996-06-01), Okajima
patent: 5654572 (1997-08-01), Kawase

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