Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-03-03

2000-03-21

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

36523003, G11C 1300

Patent

active

06041006&

ABSTRACT:
A semiconductor device is disclosed that includes blocks (101-104) having normal cell arrays and redundant cell arrays. An R/N switchover setting circuit (140) includes, in one embodiment, a plurality of normally conducting transistors arranged in series. A redundancy determination circuit (120) receives an address and determines whether or not a redundancy cell array is to be used. When a redundancy cell array is to be used, the redundancy determination circuit (120) outputs not only an active YPR signal, but also the current column-wise position of the defective cell array. The position information is applied to the switchover setting circuit (140) through a redundancy position decoder (130). The switchover setting circuit (140) generates switching signals DSW based on the received column positions, and outputs the signals to the R/N switching circuit (150). The switching circuit (150) switches and connects, on the basis of the received signals, the I/O lines of an input/output section to selected normal cell arrays and a redundant cell array, bypassing the defective cell array.

REFERENCES:
patent: 5691946 (1997-11-01), DeBrosse et al.

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