Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1981-01-12

1984-01-17

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

365205, G11C 1140, G11C 700

Patent

active

044266871

ABSTRACT:
At least one taper isolated dynamic RAM cell and at least one dummy cell are provided. Between the RAM cell and the dummy cell a flip-flop sensing amplifier is connected. The dummy cell has a conductance which is half the sum of the conductance G.sub.1 of the RAM cell which corresponds to binary digit "1" and the conductance G.sub.0 of the RAM cell which corresponds to binary digit "0". Using the conductance of the dummy cell as a reference, the flip-flop sensing amplifier detects and read data from the RAM cell.

REFERENCES:
patent: 3959781 (1976-05-01), Mehta et al.
patent: 4192014 (1980-03-01), Craycraft
patent: 4270189 (1981-05-01), Brossard et al.
patent: 4270190 (1981-05-01), Jindra et al.
patent: 4291391 (1981-09-01), Chatterjee et al.
Krick "Self-Differential Sensing of MNOSMemory Arrays", vol. 16, No. 12, 5/74, pp. 4098-4099, IBM Tech. Disc. Bul.
Krick, "Dual-Level Sense Scheme for Composite Insulator Memory Arrays", IBM Tech. Disc. Bul., vol. 17, No. 6, 11/74, pp. 1811-1813.
Chatterjee et al ., Circuit Optimization of the Taper Isolated Dynamic Gain RAM Cell for VLSI Memories, IEEE International Solid-State Circuits Conference 22-27, (Feb. 14, 1979).

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