Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

36518901, 365210, G11C 1300

Patent

active

057152020

ABSTRACT:
A semiconductor memory device includes memory cell array blocks and row spare cell groups provided for the memory cell array blocks adjacent to each other and each of the row spare cell groups having a plurality of spare cells for relieving defective memory cells in the adjacent memory cell array blocks. The row spare cell groups are shared by the plurality of adjacent memory cell array blocks, hence the spare cells are allocated corresponding to the defective cells found in the memory cell array blocks, thus enhancing a relieving rate by a redundancy circuit.

REFERENCES:
patent: 5446692 (1995-08-01), Haraguchi et al.
patent: 5450361 (1995-09-01), Iwahashi et al.

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