Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1983-06-08

1986-10-07

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

For complementary information

365205, 365230, 365227, G11C 700

Patent

active

046163425

ABSTRACT:
A semiconductor memory device comprises word lines connected to a row of memory cells, pairs of bit lines each connected to a different column of memory cells, word line drive means for driving the word line, and data sensing means. The word line drive means drives a selected word line only during a predetermined time duration which is shorter than the time duration of a word selection signal. The data sensing means includes a differential amplifier including a pair of bipolar transistors connected at their base electrodes to a pair of bit lines. Within the predetermined shorter time period, the differential amplifier senses the data stored in a selected memory cell and that sensed data is latched by a latching circuit.

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Miyamoto et al, "A 1.0 .mu.m N-Well CMOS/Bipolar Technology for VLSI Circuits", IEEE Electron Devices Meeting, Dec. 5-7, 1983, pp. 63-66.
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Ochii, et al., "A 15nW Standby Power 64Kb CMOS RAM," ISSCC Digest of Technical Paper, pp. 260-261 and 334, Feb. 12, 1982.

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