Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-04-11

2011-12-13

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Particular read circuit

C365S051000, C365S063000, C365S189170

Reexamination Certificate

active

08077530

ABSTRACT:
A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.

REFERENCES:
patent: 5793669 (1998-08-01), Sheffield et al.
patent: 6005796 (1999-12-01), Sywyk et al.
patent: 6014338 (2000-01-01), Wang et al.
patent: 6105123 (2000-08-01), Raje
patent: 6347062 (2002-02-01), Nii et al.
patent: 6452851 (2002-09-01), Endo et al.
patent: 6473350 (2002-10-01), Lee
patent: 6535453 (2003-03-01), Nii et al.
patent: 6542428 (2003-04-01), Hidaka
patent: 6807124 (2004-10-01), Tsuda et al.
patent: 6836439 (2004-12-01), Kang
patent: 6885609 (2005-04-01), Lee et al.
patent: 6985379 (2006-01-01), Nii
patent: 7075842 (2006-07-01), Tzartzanis et al.
patent: 7123504 (2006-10-01), Yabe
patent: 7139214 (2006-11-01), Atwood et al.
patent: 7301793 (2007-11-01), Kanehara et al.
patent: 7400523 (2008-07-01), Houston
patent: 7400524 (2008-07-01), Otsuka
patent: 7483332 (2009-01-01), Houston
patent: 7489570 (2009-02-01), Kim et al.
patent: 7499312 (2009-03-01), Matick et al.
patent: 7525868 (2009-04-01), Liaw
patent: 7554163 (2009-06-01), Yamada et al.
patent: 2006/0176753 (2006-08-01), Chan et al.
patent: 2006/0198204 (2006-09-01), Lambrache et al.
patent: 2007/0115710 (2007-05-01), Kim et al.
patent: 63-205890 (1988-08-01), None
patent: 2002-043441 (2002-02-01), None
patent: 2002-055130 (2002-02-01), None
patent: 2004-047003 (2004-02-01), None
patent: 2004-055130 (2004-02-01), None
Henkels, et al., “A 500 MHz 32-Word × 64-Bit 8-Port Self-Resetting CMOS Register File and Associated Dynamic-to-Static Latch, ” Symposium on VLSI Circuits Digest of Technical Papers, Watson Research Center, Yorktown Heights, NY, 1997.
Yabuuchi, M., et al., “A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations,” 2007 IEEE International Solid-State Circuits Conferences, Digest of Technical Papers, ISSCC 2007 / Session 18 / SRAM / 18.3, 2007, p. 326, 327, 606, IEEE.
Joshi, R., et al., “6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM,” 2007 Symposium on VLSI Circuits Digest of Technical Papers, 978-4-900784-04-8, 24-1, 2007, p. 250-251.
Chang, L., et al., “A 5.3GHZ 8T-SRAM with Operation Down to 0.41V in 65nm CMOS,” 2007 Symposium on VLSI Circuits Digest of Technical Papers, 978-4-900784-04-8, 24-2, 2007, p. 252-253.
Ishikura, S., et al., “A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues,” 2007 Symposium on VLSI Circuits Digest of Technical Papers, 978-4-900784-04-8, 24-3, 2007, p. 254-255.
Notice of Allowance issued in U.S. Appl. No. 12/878,534, mailed on Feb. 14, 2011.

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