Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1980-12-02

1983-08-09

Martin, John C.

Static information storage and retrieval

Systems using particular element

Semiconductive

3072388, 357 23, G11C 1140, H01L 2978

Patent

active

043982670

ABSTRACT:
A plurality of memory cells are arranged on a semiconductor substrate in the matrix form. Each memory cell comprises a first MOS field effect transistor whose drain electrode is connected to a read bit line, and whose source electrode is connected to a read word line, and a second MOS field effect transistor whose source electrode is connected to the gate electrode of the first MOS field effect transistor, and whose drain electrode is connected to a write bit line, and whose gate electrode is connected to a write word line. The first MOS field effect transistor is formed in the surface region of the semiconductor substrate and the second MOS field effect transistor is formed of a polycrystalline silicon layer, which is deposited on the semiconductor substrate with an oxide layer interposed therebetween to act as the gate region of the first MOS field effect transistor.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 4139786 (1979-02-01), Raymond et al.

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