Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S189070

Reexamination Certificate

active

08059481

ABSTRACT:
A semiconductor memory device includes a memory cell array provided with a main memory cell array including a plurality of memory cells, and a dummy column including a plurality of dummy memory cells, a dummy readout current control section configured to control a current value of a dummy readout current of the dummy memory cell in such a manner that the current value becomes between the current values of the readout currents in first and second states of the memory cell, and a sense section provided with a sense amplifier configured to receive a readout current in one of the first and second states, or dummy readout current as an input, comparing these currents with each other, and outputting the currents.

REFERENCES:
patent: 6069831 (2000-05-01), Jang et al.
patent: 2003/0202412 (2003-10-01), Nii et al.
patent: 2004/0042275 (2004-03-01), Yoshizawa et al.
patent: 06-036586 (1994-02-01), None
Fackenthal et al, A 3.3V 16Mbit DRAM-Compatible Flash Memory, Symposium on VLSI Circuit Digest of Technical Papers, Jun. 1995, pp. 62-68.

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