Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Amorphous

Reexamination Certificate

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C365S113000

Reexamination Certificate

active

08085585

ABSTRACT:
A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

REFERENCES:
patent: 2004/0042313 (2004-03-01), Fricke et al.
patent: 2008/0002455 (2008-01-01), Toda et al.
patent: 2008/0002456 (2008-01-01), Toda et al.
patent: 2008/0002457 (2008-01-01), Toda et al.
patent: 2008/0258129 (2008-10-01), Toda
patent: 2001-168294 (2001-06-01), None
patent: 2006-279042 (2006-10-01), None
patent: 2006-294179 (2006-10-01), None

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