Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2009-12-17

2011-12-06

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000

Reexamination Certificate

active

08072833

ABSTRACT:
A semiconductor memory device includes a first write bit line, a second write bit line, a write word line, a first read bit line, a read word line, and a memory cell array including a plurality of memory cells, and arranged the plurality of memory cells in a matrix fashion, wherein the memory cells including a first inverter including a first PMOS transistor and a first NMOS transistor, a second inverter including a second PMOS transistor, and a second NMOS transistor, and including an input terminal and an output terminal connected to an output terminal and an input terminal of the first inverter, respectively, a first write transfer transistor connected between a first write bit line and the output terminal of the first inverter, and including a gate connected to a write word line, a second write transfer transistor connected between a second write bit line and the output terminal of the second inverter, and including a gate connected to the write word line, a first read driver transistor including a gate connected to the input terminal of any one of the first inverter and the second inverter, and a first read transfer transistor connected to a first read bit line through the first read driver transistor, and including a gate connected to a read word line, the first read transfer transistor shared by at least two of the memory cells in the memory cell array.

REFERENCES:
patent: 6711086 (2004-03-01), Terada
patent: 7986547 (2011-07-01), Hirabayashi
patent: 2005/0152204 (2005-07-01), Lee et al.
patent: 2007/0139997 (2007-06-01), Suzuki et al.
patent: 2007/0195584 (2007-08-01), Imai et al.
patent: 07-240095 (1995-09-01), None
patent: 11-007773 (1999-01-01), None
H. Noguchi et al., “Which is the Best Dual-Port SRAM in 45-nm Process Technology?—8T, 10T Single End, and 10T Differential—”ICICDT IEEE, Jun. 2-4, 2008, pp. 55-58.
Explanation of Non-English Language References.

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