Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S163000, C365S189070, C365S230030

Reexamination Certificate

active

08068358

ABSTRACT:
A semiconductor memory device comprising: a plurality of cell arrays having a plurality of first wirings and a plurality of second wirings intersecting each other and memory cells disposed at intersections between said first wirings and said second wirings, each containing a variable resistive element that is electrically rewritable and stores a resistance value as data; and a control circuit for selectively driving said first wirings and said second wirings; wherein said control circuit performs a first operation of applying a voltage required for one operation selected from the data write, read and erase operations to said one memory cell via one combination of said first and second wirings and a second operation of applying a voltage required for an operation selected from the data write, read and erase operations and different from the first operation to said other memory cell via another combination of said first and second wirings.

REFERENCES:
patent: 2007/0211551 (2007-09-01), Yogev et al.
patent: 2008/0112211 (2008-05-01), Toda
patent: 2008/0144363 (2008-06-01), Lee et al.
patent: 2008/0310211 (2008-12-01), Toda et al.
patent: 2009/0052234 (2009-02-01), Nakai
patent: 2009/0141567 (2009-06-01), Lee et al.
patent: 2009/0201710 (2009-08-01), Ueda
patent: 2009/0213646 (2009-08-01), Choi et al.
patent: 2010/0103723 (2010-04-01), Kawai et al.
patent: 2010/0195362 (2010-08-01), Norman
patent: 2010/0259966 (2010-10-01), Kanzawa et al.
patent: 2010/0259970 (2010-10-01), Toda et al.
patent: 2011/0019462 (2011-01-01), Toda
U.S. Appl. No. 12/370,111, filed Feb. 12, 2009, Hiroshi Maejima, et al.

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