Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2008-09-10
2011-11-22
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S764000, C365S200000
Reexamination Certificate
active
08065589
ABSTRACT:
A semiconductor memory device includes a memory cell array from which all bits of a data signal having a first number of the bits composed of a main data signal and an error detection/correction code data signal are simultaneously read, a sense amplifier for amplifying the read data signal, a selection unit for selecting a data signal having a second number of bits forming a part of the data signal amplified by the sense amplifier, and an error detection/correction unit for performing error detection and correction based on at least a part of the selected data signal having the second number of bits, wherein the selection by the selection unit is performed based on a row address.
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Japanese Notice of Reasons for Rejection, w/ English translation thereof, issued in Japanese Patent Application No. JP 2007-260850 dated Feb. 1, 2011.
Gaffin Jeffrey A
McDermott Will & Emery LLP
Nguyen Steve
Panasonic Corporation
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