Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2009-03-26

2011-12-27

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S226000

Reexamination Certificate

active

08085579

ABSTRACT:
In a memory cell, a margin for data preservation is provided while suppressing a current consumption associated with a low-power consumption mode. A MOS transistor has the same structure as NMOS transistors included in each of memory cells. When a low-power consumption mode is designated, a voltage developed at a node is stabilized by subtracting a margin voltage for data preservation across a first resistor from a voltage applied to a first node and by subtracting a threshold voltage of the MOS transistor from the resultant voltage is applied to a second node.

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Office Action dated Nov. 16, 2010 in corresponding JP patent application No. 2008-295502 (English translation enclosed).
The Reason for Rejection issued from the Japanese Patent Office on Feb. 2, 2010 in the corresponding Japanese patent application No. 2008-295502 (with English translation thereof).

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