Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-10-10
2011-11-01
Trimmings, John (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S025000, C714S048000, C714S719000, C714S720000, C714S733000, C365S200000, C365S201000, C365S189150, C365S210100, C365S203000, C365S230030, C365S145000
Reexamination Certificate
active
08051342
ABSTRACT:
A semiconductor memory device including: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions where the plurality of word lines and the plurality of bit lines intersect with each other; a plurality of data bus lines connected to the plurality of bit lines; a plurality of sense amplifiers individually connected to the plurality of data bus lines and configured for detecting memory data stored in corresponding memory cells based on values of currents that are generated in the individual data bus lines in accordance with the memory data.
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Arent & Fox LLP
Fujitsu Semiconductor Limited
Trimmings John
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