Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-09-27
1994-10-04
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 371 102, G11C 700, G11C 1140
Patent
active
053532538
ABSTRACT:
A smaller, high-speed, semiconductor memory device having redundancy is disclosed which attains an improved mass productivity. Where a main memory (20) includes a defective memory cell, a defective address designating circuit (21) stores the address of the defective memory cell. Defective address detecting circuits (22a to 22r) detect whether an address signal received at an address signal input terminal (4) coincides with an address signal from the defective address designating circuit (21). If a signal indicative of the coincidence is given to a redundancy memory circuit (23) from the defective address detecting circuits (22a to 22r), data is written in or read from defective address remedy latch circuit groups (23a to 23r) of the redundancy memory circuit (23) which correspond to the defective address detecting circuits (22a to 22r). A data selector (24) selectively outputs data received from the defective address remedy latch circuit groups (23a to 23r) or data received from the main memory (20). Thus, the redundancy memory circuit (23), which requires less space, quickly replaces the defective memory cell of the main memory (20).
REFERENCES:
patent: 4376300 (1993-03-01), Tsang
patent: 4428068 (1984-01-01), Baba
patent: 4744060 (1988-05-01), Okajima
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 5179536 (1993-01-01), Kasa et al.
patent: 5206831 (1993-04-01), Wakamatsu
Dinh Son
LaRoche Eugene R.
Mitsubishi Denki & Kabushiki Kaisha
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