Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2010-01-05

2011-12-20

Hidalgo, Fernando N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S194000, C365S233100, C365S149000, C365S150000, C365S186000, C365S189011, C365S233120

Reexamination Certificate

active

08081533

ABSTRACT:
A semiconductor memory device is provided between a refresh request circuit and a command decoder, and includes a refresh synchronous circuit for deactivating a refresh request if an external access request is output from the command decoder. The semiconductor memory device further includes a clock phase adjusting unit that generates a delay to a clock, where the delay is same or longer than the time taken from when the external access request is issued until when a critical path is passed, and the delay is also shorter than one cycle. Then a flip-flop retrieves the request from the command decoder at the clock timing from the clock phase adjusting unit to supply it to the memory cell array.

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patent: 6981187 (2005-12-01), Oh
patent: 7200059 (2007-04-01), Fujioka et al.
patent: 7505346 (2009-03-01), Kobayashi
patent: 7652941 (2010-01-01), Mori et al.
patent: 3376998 (2002-12-01), None

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