Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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Details

C365S189030, C365S189080, C365S063000, C365S051000, C365S202000, C365S207000, C365S189170

Reexamination Certificate

active

08050127

ABSTRACT:
A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

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Notice of Allowance issued from Korean Intellectual Property Office on May 31, 2011.

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