Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-12-13

2010-06-01

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S226000, C365S230010

Reexamination Certificate

active

07729180

ABSTRACT:
A semiconductor memory device operates using a first power supply and a second power supply. The device includes a static memory cell which receives the first power supply, a word line which is connected to the memory cell, and a decoder which controls selection/deselection of the word line on the basis of an address signal having a voltage of the second power supply. The decoder includes a level shifter which changes a voltage of the word line to a voltage of the first power supply, and a switching circuit which receives the first power supply and applies a voltage lower than the first power supply to the level shifter in selecting the word line.

REFERENCES:
patent: 2002/0163841 (2002-11-01), Taura et al.
patent: 2003/0098711 (2003-05-01), Tsuboi et al.
patent: 2007/0036017 (2007-02-01), Seo
Muhammad Khellah, et al., “A 4.2GHz 0.3mm2256kb Dual-VccSRAM Building Block in 65nm CMOS”, 2006 IEEE International Solid-State Circuits Conference (ISSCC 2006), Digest of Technical Papers, Session 34, SRAM, 34.2, Feb. 8, 2006, 10 Pages.

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