Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-09-10

2010-06-29

Dinh, Son (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189150, C257S351000

Reexamination Certificate

active

07746685

ABSTRACT:
SRAM cells are arranged in matrix along a first and a second bit line and a word line for single-ended reading of data from the second bit line. A first NMOS transistor and a first transfer transistor contained in the SRAM cell are formed in a first well with respective identical gate lengths and gate widths. A second NMOS transistor and a second transfer transistor contained in the SRAM cell are formed in a second well with respective identical gate lengths and gate widths. These gate widths are made wider than the gate widths of the first NMOS transistor and the first transfer transistor.

REFERENCES:
patent: 6363006 (2002-03-01), Naffziger et al.
patent: 7400524 (2008-07-01), Otsuka
patent: 2-151066 (1990-06-01), None
patent: 2001-28401 (2001-01-01), None
patent: 2003-86713 (2003-03-01), None
U.S. Appl. No. 12/343,996, filed Dec. 24, 2008, Kawasumi.

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