Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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Details

C365S225700

Reexamination Certificate

active

07859923

ABSTRACT:
The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.

REFERENCES:
patent: 6178125 (2001-01-01), Niiro
patent: 7411845 (2008-08-01), Kodama
patent: 2001-023393 (2001-01-01), None

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