Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-02-23

1997-09-09

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Testing

365222, G11C 1140

Patent

active

056663170

ABSTRACT:
When a disturb refresh mode is detected by a mode detecting circuit, a row decoder control circuit simultaneously activates every several word lines of a memory cell array of a block selected by an operation block selecting circuit through a row decoder and a driving circuit, reads out data written in a normal mode, and determines a memory cell having a threshold value lower than that of a design value upon determination of match of read data and written data.

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