Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-07-05

2010-06-22

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S005110, C714S025000, C714S042000, C714S719000, C714S724000, C714S726000, C714S727000, C714S729000, C714S742000, C365S201000

Reexamination Certificate

active

07743291

ABSTRACT:
A semiconductor memory device includes a memory cell array, a plurality of data input/output terminals, a plurality of signal paths for writing data supplied to the data input/output terminals to the memory cell array in parallel, a plurality of latch circuits temporarily holding the data on the signal paths, respectively, and a selector selectively supplying the data to the latch circuits from a test data terminal during a test operation. The data can be thereby supplied from the test data terminal to the latch circuits in parallel during the test operation. The number of terminals used at an operation test can be, therefore, greatly decreased.

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