Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S049130

Reexamination Certificate

active

07830739

ABSTRACT:
A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit block and the row of sense amplifiers attached to the unit block; and control means for controlling the switch means so as to form a transfer path from the row of sense amplifiers attached to a predetermined the unit block leading to the row of sense amplifiers as a saving destination not attached to the predetermined the unit block. This row of sense amplifiers attached to the predetermined the unit block functions as a cache memory.

REFERENCES:
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patent: 5706244 (1998-01-01), Shimizu
patent: 5774408 (1998-06-01), Shirley
patent: 7193875 (2007-03-01), Kim
patent: 2004/0184304 (2004-09-01), Kajigaya et al.
patent: 5-159566 (1993-06-01), None
patent: 5-159567 (1993-06-01), None
patent: 5-182452 (1993-07-01), None
patent: 8-129877 (1996-05-01), None
patent: 2004-103657 (2004-04-01), None
Japanese Office Action dated Jul. 22, 2008.

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