Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-08-07

2010-10-05

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S145000

Reexamination Certificate

active

07808846

ABSTRACT:
A semiconductor memory device to/from which a data signal is input/output in synchronism with a clock, including: an input signal delaying circuit for delaying an input signal to output the delayed input signal; a delayed clock generation circuit for delaying an input clock by different amounts of delay time to thereby generate a plurality of delayed clocks; a plurality of delayed input signal holding circuits for holding the delayed input signal on the plurality of delayed clocks, respectively; an input signal latch timing determination circuit for outputting a determination signal indicating a timing at which to latch the delayed input signal, based on a plurality of held signals held by the delayed input signal holding circuits; and a held signal selector circuit for integrating the plurality of held signals into a single signal.

REFERENCES:
patent: 4415984 (1983-11-01), Gryger et al.
patent: 5801562 (1998-09-01), Fujii
patent: 6829316 (2004-12-01), Terada et al.
patent: 2007/0058479 (2007-03-01), Matsui
patent: 8-102729 (1996-04-01), None
patent: 3146117 (2001-01-01), None
patent: 2001-154907 (2001-06-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4184001