Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-12-12

2010-06-15

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S063000, C365S207000

Reexamination Certificate

active

07738312

ABSTRACT:
One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.

REFERENCES:
patent: 6538954 (2003-03-01), Kunikiyo
patent: 7285832 (2007-10-01), Hoefler et al.
patent: 7652927 (2010-01-01), Morishita et al.
Hidaka, H., et al., “A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's”, IEEE Journal of Solid-State Circuits, Apr. 1992, pp. 610-617, vol. 27 No. 4, IEEE.
Agata, Y., et al., “An 8-ns Random Cycle Embedded RAM Macro With Dual-Port Interleaved DRAM Architecture (D2RAM)”, IEEE Journal of Solid-State Circuits, Nov. 2000, pp. 1668-1672, vol. 35 No. 11, IEEE.
Morishita, F., et al., “A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI”, IEEE 2005 Custom Integrated Circuits Conference, 2005, pp. 435-438.
Arimoto, K., et al., “A Configurable Enhanced T2RAM Macro for System-Level Power Management Unified Memory”, 2006 Symposium on VLSI Circuits Digest of Technical Papers, 2006.

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