Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-10-11

2010-10-12

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S718000, C714S736000

Reexamination Certificate

active

07814381

ABSTRACT:
A semiconductor memory device is adapted so that access time can be measured accurately when the device is in a test mode. A read or write operation of a memory array in the normal mode is performed in accordance with a first signal, a read or write operation of the memory array in the test mode is performed in accordance with a second signal, and a test of a plurality of items of output data from the memory array is conducted in the test mode and results of the test are output. It is so arranged that a desired test is conducted in the test mode based upon a third signal unrelated to the first signal and second signal.

REFERENCES:
patent: 4868823 (1989-09-01), White et al.
patent: 6189121 (2001-02-01), Ogawa
patent: 6304502 (2001-10-01), Watanabe et al.
patent: 7558993 (2009-07-01), Park et al.
patent: 09-166646 (1997-06-01), None
patent: 2001-332099 (2001-11-01), None

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