Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S189120, C365S189020

Reexamination Certificate

active

07742349

ABSTRACT:
A circuit can control a bit rate of information output from a multi-purpose register (MPR) of a semiconductor memory device in a test mode, thereby reducing current consumption for outputting information in a multi-purpose register (MPR). The semiconductor memory device includes a multi-purpose register configured separately to store a plurality of information, and to control a bit rate of the stored information in a test mode, each of the information having multiple bits, and a connection selector configured selectively to connect an output terminal of the multi-purpose register to one of a number of global lines according to an operation mode.

REFERENCES:
patent: 6898139 (2005-05-01), Lee et al.
patent: 2006/0010292 (2006-01-01), DeVale et al.
patent: 2007/0168631 (2007-07-01), Heo
patent: 2001-256062 (2001-09-01), None
patent: 2004-362215 (2004-12-01), None
patent: 1020040104903 (2004-12-01), None
patent: 100719181 (2007-05-01), None
patent: 100719377 (2007-05-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Aug. 28, 2009 with an English Translation.

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