Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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Details

C365S230030, C365S230060

Reexamination Certificate

active

07663956

ABSTRACT:
A semiconductor memory device performs a refresh operation sequentially for a word line selected based on a row address when receiving a refresh request, and comprises: a memory cell array divided into M banks; a refresh counter for sequentially outputting a count value corresponding to the word line to be refreshed in response to the refresh request; and a row address converter for supplying row addresses different from one anther in at lest two banks among the M banks by converting the count value. In the semiconductor memory device, a predetermined number of selected word lines are refreshed at the same time in the banks in accordance with different patterns from one another, and the maximum value of the total number of the selected word lines refreshed at the same time for all the M banks is controlled to be lower than 2M.

REFERENCES:
patent: 5991218 (1999-11-01), Kushiyama
patent: 6888776 (2005-05-01), Watanabe et al.
patent: 2003/0112689 (2003-06-01), Natsui et al.
patent: 2007/0076504 (2007-04-01), Suh
patent: 7-122065 (1995-05-01), None
patent: 11-39861 (1999-02-01), None
patent: 2003-187578 (2003-07-01), None

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